A hardware feature of some pipeline architectures that allows the result of an operation to be used immediately as an operand for a second operation, simultaneously with the writing of the result to its destination register. The total cycle time of two chained operations is less than the sum of the stand-alone cycle times for the instructions. For example, the TI 8847 supports chaining of consecutive fadd, fsub, and fmul (of the same precision). Chained faddd/fmuld requires 12 cycles, while consecutive unchained faddd/fmuld requires 17 cycles.